Reduction Method of Number of Electromagnetic Simulation Times for Estimationg Output Voltage at Hard Open TSV in 3D IC

Reduction Method of Number of Electromagnetic Simulation Times for Estimationg Output Voltage at Hard Open TSV in 3D IC

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Veröffentlicht in:2013 IEEE CPMT Symposium Japan (formerly VLSI Packaging Workshop of Japan)
1. Verfasser: Haraguchi, Ei (VerfasserIn)
Weitere Verfasser: Hashizume, Masaki (VerfasserIn), Manabe, Katsuya (VerfasserIn), Yotsuyanagi, Hiroyuki (VerfasserIn), Tada, Tetsuo (VerfasserIn), Lu, Shyue-Kung (VerfasserIn), Roth, Zvi (VerfasserIn)
Pages:2013
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Sprache:eng
Veröffentlicht: 2013
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