Three-dimensional Integration Scheme using Hybrid Wafer Bonding and Via-last TSV Process

Three-dimensional Integration Scheme using Hybrid Wafer Bonding and Via-last TSV Process

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Veröffentlicht in:2012 2nd IEEE CPMT Symposium Japan
1. Verfasser: Takeda, Kenichi (VerfasserIn)
Weitere Verfasser: Aoki, Mayu (VerfasserIn), Hozawa, Kazuyuki (VerfasserIn), Furuta, Futoshi (VerfasserIn), Yanagisawa, Azusa (VerfasserIn), Kikuchi, Hidekazu (VerfasserIn), Mitsuhashi, Toshio (VerfasserIn), Kobayashi, Harufumi (VerfasserIn)
Pages:2012 2
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Sprache:eng
Veröffentlicht: 2012
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