Design and test technology for dependable systems-on-chip
"This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"--
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| Weitere Verfasser: | , , |
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| Format: | UnknownFormat |
| Sprache: | eng |
| Veröffentlicht: |
Hershey, Pa. u.a.
Information Science Reference/IGI Global
2011
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| Schriftenreihe: | Premier reference source
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| Schlagworte: | |
| Online Zugang: | Inhaltsverzeichnis Leseproben |
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Tag hinzufügen | Zusammenfassung: | "This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"-- |
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| Beschreibung: | Includes bibliographical references and index Editors: Raimund Ubar (Tallinn University of Technology, Estonia); Jaan Raik (Tallinn University of Technology, Estonia); Heinrich Theodor Vierhaus (Brandenburg University of Technology Cottbus, Germany) |
| Beschreibung: | XXVI, 550 S. Ill., graph. Darst. |
| ISBN: | 1609602129 1-60960-212-9 9781609602123 978-1-60960-212-3 |