Power distribution networks with on-chip decoupling capacitors
Cover -- TOC - Contents -- CH.1 Introduction -- 1.1 Evolution of integrated circuit technology -- 1.2 Evolution of design objectives -- 1.3 The problem of power distribution -- 1.4 Deleterious effects of power distribution noise -- 1.4.1 Signal delay uncertainty -- 1.4.2 On-chip clock jitter -- 1.4....
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Weitere Verfasser: | , |
| Format: | UnknownFormat |
| Sprache: | eng |
| Veröffentlicht: |
New York, NY
Springer
c 2008
|
| Schlagworte: | |
| Online Zugang: | Inhaltsverzeichnis Verlagsangaben Cover |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Tag hinzufügen 
| Zusammenfassung: | Cover -- TOC - Contents -- CH.1 Introduction -- 1.1 Evolution of integrated circuit technology -- 1.2 Evolution of design objectives -- 1.3 The problem of power distribution -- 1.4 Deleterious effects of power distribution noise -- 1.4.1 Signal delay uncertainty -- 1.4.2 On-chip clock jitter -- 1.4.3 Noise margin degradation -- 1.4.4 Degradation of gate oxide reliability -- 1.5 Book outline -- CH.2 Inductive Properties of Electric Circuits -- 2.1 Definitions of inductance -- 2.1.1 Field energy definition -- 2.1.2 Magnetic flux definition -- 2.1.3 Partial inductance -- 2.1.4 Net inductance -- 2.2 Variation of inductance with frequency -- 2.2.1 Uniform current density approximation -- 2.2.2 Inductance variation mechanisms -- 2.2.3 Simple circuit model -- 2.3 Inductive behavior of circuits -- 2.4 Inductive properties of on-chip interconnect -- 2.5 Summary -- CH.3 Properties of On-Chip Inductive Current Loops -- 3.1 Introduction -- 3.2 Dependence of inductance on line length -- 3.3 Inductive coupling between two parallel loop segments -- 3.4 Application to circuit analysis -- 3.5 Summary -- CH.4 Electromigration -- 4.1 Physical mechanism of electromigration -- 4.2 Electromigration-induced mechanical stress -- 4.3 Steady state limit of electromigration damage -- 4.4 Dependence of electromigration lifetime on the line dimensions -- 4.5 Statistical distribution of electromigration lifetime -- 4.6 Electromigration lifetime under AC current -- 4.7 Electromigration in novel interconnect technologies -- 4.8 Designing for electromigration reliability -- 4.9 Summary -- CH.5 High Performance Power Distribution Systems -- 5.1 Physical structure of a power distribution system -- 5.2 Circuit model of a power distribution system -- 5.3 Output impedance of a power distribution system -- 5.4 A power distribution system with a decoupling capacitor -- 5.4.1 Impedance characteristics -- 5.4.2 Limitations of a single-tier decoupling scheme -- 5.5 Hierarchical placement of decoupling capacitance -- 5.6 Resonance in power distribution networks -- 5.7 Full impedance compensation -- 5.8 Case study -- 5.9 Design considerations -- 5.9.1 Inductance of the decoupling capacitors -- 5.9.2 Interconnect inductance -- 5.10 Limitations of the one-dimensional circuit model -- 5.11 Summary -- CH.6 Decoupling Capacitance -- 6.1 Introduction to decoupling capacitance -- 6.1.1 Historical retrospective -- 6.1.2 Decoupling capacitor as a reservoir of charge -- 6.1.3 Practical model of a decoupling capacitor -- 6.2 Impedance of power distribution system with decoupling capacitors -- 6.2.1 Target impedance of a power distribution system -- 6.2.2 Antiresonance -- 6.2.3 Hydraulic analogy of hierarchical placement of decoupling capacitors -- 6.3 Intrinsic vs intentional on-chip decoupling capacitance -- 6.3.1 Intrinsic decoupling capacitance -- 6.3.2 Intentional decoupling capacitance -- 6.4 Types of on-chip decoupling capacitors -- 6.4.1 Polysilicon-insulator-polysilicon (PIP) capacitors -- 6. |
|---|---|
| Beschreibung: | Literaturverz. S. [485] - 507 |
| Beschreibung: | XXXII, 515 S. Ill., graph. Darst. 235 mm x 155 mm |
| ISBN: | 0387716009 0-387-71600-9 9780387716008 978-0-387-71600-8 |