Design and FPGA Synthesis of an Efficient Synchronous Counter with Clock-Gating Techniques

Design and FPGA Synthesis of an Efficient Synchronous Counter with Clock-Gating Techniques

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Veröffentlicht in:NCCS-2019 (5. : 2019 : Ranchi) Nanoelectronics, circuits and communication systems
1. Verfasser: Singh, Saurabh Kumar (VerfasserIn)
Weitere Verfasser: Gupta, Mangal Deep (VerfasserIn), Chauhan, R. K. (VerfasserIn)
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Sprache:eng
Veröffentlicht: 2021
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