Power-Delay-Area Efficient Design and Implementation of Vedic Multiplier Using 14 nm Finfet Technology

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Veröffentlicht in:ICCCE (4. : 2021 : Hyderabad) ICCCE 2021 ; Volume 2
1. Verfasser: Shetkar, Swati (VerfasserIn)
Weitere Verfasser: Waje, Manisha (VerfasserIn)
Pages:2021
Format: UnknownFormat
Sprache:eng
Veröffentlicht: 2022
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