On-chip networks

This book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short synthesis of the most critical concepts in on-chip network design. It is a resource for both understanding on-chip...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: Enright Jerger, Natalie D. (VerfasserIn)
Weitere Verfasser: Krishna, Tushar (VerfasserIn), Peh, Li-Shiuan (VerfasserIn)
Format: UnknownFormat
Sprache:eng
Veröffentlicht: San Rafael, California Morgan & Claypool Publishers 2017
Ausgabe:Second edition
Schriftenreihe:Synthesis lectures on computer architecture 40
Schlagworte:
Online Zugang:Inhaltsverzeichnis
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Beschreibung
Zusammenfassung:This book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short synthesis of the most critical concepts in on-chip network design. It is a resource for both understanding on-chip network basics and for providing an overview of state of-the-art research in on-chip networks. We believe that an overview that teaches both fundamental concepts and highlights state-of-the-art designs will be of great value to both graduate students and industry engineers. While not an exhaustive text, we hope to illuminate fundamental concepts for the reader as well as identify trends and gaps in on-chip network research. With the rapid advances in this field, we felt it was timely to update and review the state of the art in this second edition. We introduce two new chapters at the end of the book. We have updated the latest research of the past years throughout the book and also expanded our coverage of fundamental concepts to include several research ideas that have now made their way into products and, in our opinion, should be textbook concepts that all on-chip network practitioners should know. For example, these fundamental concepts include message passing, multicast routing, and bubble flow control schemes
Beschreibung:Includes bibliographical references (pages 151-188)
Beschreibung:XIX, 190 Seiten
illustrations
24 cm
ISBN:1627059148
1-62705-914-8
9781627059145
978-1-62705-914-5