Highly Reliable 100nm Buried-Channel-pMOSFET for Embedded-LSIs

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Bibliographische Detailangaben
Veröffentlicht in:	Handōtai-Shūseki-Kairo-Gijutsu-Shinpojiumu (59 : 2000 : Tokio) Handōtai, Shuseki-Kairo-Gijutsu-59.-Shinpojiumu-kōen-ronbunshū
1. Verfasser:	Nishida, Y. (VerfasserIn)
Weitere Verfasser:	Sayama, H. (VerfasserIn), Oda, H. (VerfasserIn), Inooue, Y. (VerfasserIn), Inuishi, M. (VerfasserIn)
Pages:	59
Format:	UnknownFormat
Sprache:	jpn
Veröffentlicht:	2000
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Titel	Jahr	Verfasser
Issues and Prospects for High Performance 0.1 μ m Devices	2000	Takeuchi, K.
Impacts of Residual Chlorine in CVD-TiN Gate Electrode on the Gate Oxide Relhiability	2000	Moriwaki, M.
Barrier Layers for Copper Interconnections	2000	Hara, T.
Self lon Sputtering Technoligy of Barrier and Cu Seed Layers for Cu Damascene Interconnects	2000	Katata, T.
High Performance CMOS Technology for Large Scale System-on-a-chip in 130-nm Node	2000	Onai, T.
Super MOSFET using high K Gate Dielectric or SiGe	2000	Chin, Albert
Microstructure of Cu Interconnect Lines	2000	Okabayashi, H.
Evaluation of Low-k Dielectric Materials in Ashing Process	2000	Nishida, T.
Integrity of Copper Diffusion Barrier Metal	2000	Komai, N.
A 70nm High Performance CMOS Technology with 1.0V Operation	2000	Ono, A.
Adhesion and Agglomeration of Cu-CVD Films	2000	Vezin, V.
Highly Reliable 100nm Buried-Channel-pMOSFET for Embedded-LSIs	2000	Nishida, Y.
Investigation of the MIS structure with Gate Dielectrics used Zr-related Materials	2000	Yamaguchi, T.
Wafer Edge Etching of Electrode and Interconnection Materials	2000	Katakabe, I.
Additive Effects of Hole and Gap Filling Mechanism in Copper Electroplating	2000	Haba, T.