How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization
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2019 |
Netto, Renan |
Device Layer-Aware Analytical Placement for Analog Circuits
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2019 |
Xu, Biying |
FPGA-based Computing in the Era of Al and Big Data
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2019 |
Nurvitadhi, Eriko |
Improving Programmability and Efficiency of Large-Scale Graph Analytics for FPGA Platforms
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2019 |
Ozdal, Muhammet Mustafa |
Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints
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2019 |
Ryzhenko, Nikolay |
ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques
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2019 |
Park, Dongwon |
Basic and Advanced Researches in Logic Synthesis and their Industrial Contributions
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2019 |
Fujita, Masahiro |
My 50-Year Journey from Punched Cards to Swarm Systems
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2019 |
Vincentelli, Alberto Sangiovanni |
Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach
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2019 |
Sharma, Ankur |
ISPD 2019 Initial Detailed Routing Contest and Benchmarks 147 with Advanced Routing Rules
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2019 |
Liu, Wen-Hao |
Fusion: The Dawn of the Hyperconvergence Era in EDA
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2019 |
Krishnamoorthy, Shankar |
Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement Minimization
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2019 |
Li, Xingquan |
Advances in Adaptable Computing
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2019 |
Gupta, Amit |
PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONOCS.
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2019 |
Truppel, Alexandre |
Electromigration-Aware Interconnect Design
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2019 |
Sapatnekar, Sachin S. |
From Electronic Design Automation to Automotive Design Automation
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2019 |
Lin, Chung-Wei |
From Electronic Design Automation to Cyber-Physical System Design Automation: A Tale of Platforms and Contracts
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2019 |
Nuzzo, Pierluigi |
Freedom From Choice and the Power of Models: In Honor of Alberto Sangiovanni-Vincentelli
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2019 |
Lee, Edward A. |
Analog Layout Synthesis: Are We There Yet?
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2019 |
Mangalagiri, Prasanth |
Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM Yield Analysis
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2019 |
Shi, Xiao |