3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model

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Veröffentlicht in:IFIP/IEEE International Conference on Very Large Scale Integration (28. : 2020 : Online) VLSI-SoC: design trends
1. Verfasser: Poittevin, Arnaud (VerfasserIn)
Weitere Verfasser: Mukherjee, Chhandak (VerfasserIn), O’Connor, Ian (VerfasserIn), Maneux, Cristell (VerfasserIn), Larrieu, Guilhem (VerfasserIn), Deng, Marina (VerfasserIn), Beux, Sebastien Le (VerfasserIn), Marc, Francois (VerfasserIn), Lecestre, Aurelie (VerfasserIn), Marchand, Cedric (VerfasserIn), Kumar, Abhishek (VerfasserIn)
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Sprache:eng
Veröffentlicht: 2021
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