Learning Based Timing Closure on Relative Timed Design

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IFIP/IEEE International Conference on Very Large Scale Integration (28. : 2020 : Online) VLSI-SoC: design trends
1. Verfasser: Sharma, Tannu (VerfasserIn)
Weitere Verfasser: Kolluru, Sumanth (VerfasserIn), Stevens, Kenneth S. (VerfasserIn)
Format: UnknownFormat
Sprache:eng
Veröffentlicht: 2021
Schlagworte:
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Titel Jahr Verfasser
Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 am FDSOl 2021 Cordova, David
Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring 2021 Dai, Shanshan
Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics 2021 Crafton, Brian
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation 2021 Ajayi, Tutu
Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform 2021 Veronesi, Alessandro
From Informal Specifications to an ABV Framework for Industrial Firmware Verification 2021 Germiniani, Samuele
RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique 2021 Gava, Jonas
SANSCrypt: Sporadic-Authentication-Based Sequential Logic Encryption 2021 Hu, Yinghua
3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Design 2021 Giacomin, Edouard
Learning Based Timing Closure on Relative Timed Design 2021 Sharma, Tannu
SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays 2021 Miyasaka, Yukio
abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory 2021 Eliahu, Adi
Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector 2021 Aghighi, Amin
Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication 2021 Saligram, Rakshith
Modular Functional Testing: Targeting the Small Embedded Memories in GPUs 2021 Condia, Josie Esteban Rodriguez
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model 2021 Poittevin, Arnaud
Alle Artikel auflisten