| Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks
|
2020 |
Ferianc, Martin |
| Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantized Neural Networks on FPGAs
|
2020 |
Bacchus, Pascal |
| Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices
|
2020 |
Guettatfi, Zakarya |
| HLS-Based Acceleration Framework for Deep Convolutional Neural Networks
|
2020 |
Misra, Ashish |
| A Modular Software Library or Effective High Level Synthesis of Convolutional Neural Networks
|
2020 |
Hernandez, Hector Gerardo Munoz |
| Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm
|
2020 |
Duarte, Rui P. |
| Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems
|
2020 |
Ortiz, Alberto |
| Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs
|
2020 |
Bozzoli, Ludovica |
| Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs
|
2020 |
Suriano, Leonardo |
| Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs
|
2020 |
Akgün, Gökhan |
| Technique for Vendor and Device Agnostic Hardware Area-Time Estimation
|
2020 |
Wijesundera, Deshya |
| A CGRA Definition Framework for Dataflow Applications
|
2020 |
Charitopoulos, George |
| High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-Based Post-Quantum Cryptography Using Software/Hardware Codesign
|
2020 |
Nguyen, Duc Tri |
| Comparison of Direct and Indirect Networks for High-Performance FPGA Clusters
|
2020 |
Mondigo, Antoniette |
| Chisel Usecase: Designing General Matrix Multiply for FPGA
|
2020 |
Ferres, Bruno |
| Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks
|
2020 |
Khan, Habib ul Hasan |
| Optimising Operator Sets for Analytical Database Processing on FPGAs
|
2020 |
Drewes, Anna |
| Cross-layer CNN Approximations for Hardware Implementation
|
2020 |
Ali, Karim M. A. |
| Exploring FPGA Optimizations to Compute Sparse Numerical Linear Algebra Kernels
|
2020 |
Favaro, Federico |
| A Block-Based Systolic Array on an HBM2 FPGA for DNA Sequence Alignment
|
2020 |
Abdelhamid, Riadh Ben |
Tag hinzufügen