Optimizing Accelerator on FPGA for Deep Convolutional Neural Networks

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Veröffentlicht in:ICA3PP (20. : 2020 : New York, NY; Online) Algorithms and architectures for parallel processing ; Part 2
1. Verfasser: Dong, Yong (VerfasserIn)
Weitere Verfasser: Hu, Wei (VerfasserIn), Wang, Yonghao (VerfasserIn), Jiao, Qiang (VerfasserIn), Chen, Shuang (VerfasserIn)
Pages:2
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Sprache:eng
Veröffentlicht: 2020
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