System-Level FPGA Routing for Logic Verification with Time-Division Multiplexing

System-Level FPGA Routing for Logic Verification with Time-Division Multiplexing

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Veröffentlicht in:PDCAT (21. : 2020 : Shenzhen) Parallel and distributed computing, applications and technologies
1. Verfasser: Sun, Long (VerfasserIn)
Weitere Verfasser: Guo, Longkun (VerfasserIn), Huang, Peihuang (VerfasserIn)
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Sprache:eng
Veröffentlicht: 2021
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