PPS: A Low-Latency and Low-Complexity Switching Architecture Based on Packet Prefetch and Arbitration Prediction

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Veröffentlicht in:ICA3PP (19. : 2019 : Melbourne) Algorithms and architectures for parallel processing ; Part 1
1. Verfasser: Dai, Yi (VerfasserIn)
Weitere Verfasser: Wu, Ke (VerfasserIn), Lai, Mingche (VerfasserIn), Li, Qiong (VerfasserIn), Dong, Dezun (VerfasserIn)
Pages:1
Format: UnknownFormat
Sprache:eng
Veröffentlicht: 2020
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