Multilayer ceramic substrate-technology for VLSI package/multichip module

von Ōtsuka, Kanji
Veröffentlicht 1993

Power/Ground Wiring for High Speed Driver

von Hashimoto, Kaoru
Veröffentlicht in 2013 IEEE CPMT Symposium Japan (formerly VLSI Packaging Workshop of Japan) (2013)

IO INTERFACE FOR OVER 25GBPS OPERATION WITH LOW POWER

von Otsuka, Kanji
Veröffentlicht in 2014 IEEE CPMT Symposium Japan (ICSJ 2014) (2014)

Analysis of Novel Technology for Power and Signal Integrity using a Metal Particle Conductive Layer

von Sasaoka, Norifumi
Veröffentlicht in 2014 IEEE CPMT Symposium Japan (ICSJ 2014) (2014)

A Feasibility Study of Proximity Interconnect Technology Utilizing Transmission Line Coupling

von Iguchi, Daisuke
Veröffentlicht in 2010 IEEE CPMT Symposium Japan (2010)

Study on Novel Concept of Transmission Signal Assisted with Evanescent Wave Energy

von Hashimoto, Kaoru
Veröffentlicht in 2010 IEEE CPMT Symposium Japan (2010)

Development of Touch Panel System by Single Layer without Pattern

von Sato, Yoichi
Veröffentlicht in 2013 IEEE CPMT Symposium Japan (formerly VLSI Packaging Workshop of Japan) (2013)

Fundamental Study of Direct Current Resistance Effect on Transmission Line Characteristics

von Hashimoto, Kaoru
Veröffentlicht in 2012 2nd IEEE CPMT Symposium Japan (2012)

Novel Technology for Power Integrity using by Metal Particle Conductive Layer

von Sasaoka, Norifumi
Veröffentlicht in 2012 2nd IEEE CPMT Symposium Japan (2012)

High Speed LCP Board for 28Gbps Transmission through 300mm

von Kataoka, Ryohei
Veröffentlicht in 2014 IEEE CPMT Symposium Japan (ICSJ 2014) (2014)

3D System Simulation Study of Power Integrity using Si Interposer with Distribution TSV Decoupling Capacitors

von Kohno, Kazuo
Veröffentlicht in 2012 2nd IEEE CPMT Symposium Japan (2012)

Transient Response Characteristics of Through Silicon Via in High Resistivity Silicon Interposer

von Watanabe, Naoya
Veröffentlicht in 2012 2nd IEEE CPMT Symposium Japan (2012)