Built-in IDDT Appearance Time Sensor for Detecting Open Faults in 3D IC

von Suenaga, Shohei
Veröffentlicht in 2013 IEEE CPMT Symposium Japan (formerly VLSI Packaging Workshop of Japan) (2013)

Threshold Value Estimation of Electrical Interconnect Tests with Scan FFs

von Nambara, Kousuke
Veröffentlicht in 2014 IEEE CPMT Symposium Japan (ICSJ 2014) (2014)

Reduction Method of Number of Electromagnetic Simulation Times for Estimationg Output Voltage at Hard Open TSV in 3D IC

von Haraguchi, Ei
Veröffentlicht in 2013 IEEE CPMT Symposium Japan (formerly VLSI Packaging Workshop of Japan) (2013)