Integration of Cu/low-k Dual-Damascene Interconnects with a Porous PAE/SiOC Hybrid Structure for 65nm-node High Performance eDRAM

von Kanamura, R.
Veröffentlicht in Handōtai-Shūseki-Kairo-Gijutsu-Shinpojiumu (66 : 2004 : Tokio) Handōtai, Shuseki-Kairo-Gijutsu-66.-Shinpojiumu-kōen-ronbunshū (2004)

Challenge of Low-k Materials for 65nm Mode Interconnect Technology and Beyond

von Miyajima, H.
Veröffentlicht in Handōtai-Shūseki-Kairo-Gijutsu-Shinpojiumu (68 : 2005 : Kyōto) Handōtai, Shuseki-Kairo-Gijutsu-68.-Shinpojiumu-kōen-ronbunshū (2005)