Aluminum Pillar Process for High Performance Cu Interconnects

von Kajita, A.
Veröffentlicht in Handōtai-Shūseki-Kairo-Gijutsu-Shinpojiumu (57 : 1999 : Tokio) 57.-Handōtai-Shuseki-Kairo-Gijutsu-Shinpojiumu-kōen-ronbunshū (1999)

A Study of the Electrical Resistivity Increase in Narrow and Thin Copper Interconnects

von Wada, M.
Veröffentlicht in Handōtai, Shuseki-Kairo-Gijutsu-72.-Shinpojiumu-kōen-ronbunshū (2008)

Low-Power Electronics Project & Association and Denelopment of Low-Voltage Devices

von Kimura, S.
Veröffentlicht in Handōtai, Shuseki-Kairo-Gijutsu-75.-Shinpojiumu-kōen-ronbunshū (2011)

Integration of Cu/low-k Dual-Damascene Interconnects with a Porous PAE/SiOC Hybrid Structure for 65nm-node High Performance eDRAM

von Kanamura, R.
Veröffentlicht in Handōtai-Shūseki-Kairo-Gijutsu-Shinpojiumu (66 : 2004 : Tokio) Handōtai, Shuseki-Kairo-Gijutsu-66.-Shinpojiumu-kōen-ronbunshū (2004)

Nanocarbon interconnect technology

von Sakai, T.
Veröffentlicht in Handōtai, Shuseki Kairo Gijutsu dai 78-kai Shinpojiumu kōen ronbunshū (2014)

Challenge of Low-k Materials for 65nm Mode Interconnect Technology and Beyond

von Miyajima, H.
Veröffentlicht in Handōtai-Shūseki-Kairo-Gijutsu-Shinpojiumu (68 : 2005 : Kyōto) Handōtai, Shuseki-Kairo-Gijutsu-68.-Shinpojiumu-kōen-ronbunshū (2005)