Annealing behavior of Secondary Defects in High Energy and High dose Jon-Implanted Silicon

von Kimura, K.
Veröffentlicht in Handōtai, Shūseki Kairo Gijutsu Shinpojiumu (43. : 1992 : Tokio) Handōtai, Shūseki Kairo Gijutsu Dai 43kai Shinpojiumu (1992)

Soft Error Rate Analysis Model (SERAM) for Dynamic NMOS RAMs

von AOKI, M.
Veröffentlicht in Conference on Solid State Devices (13 : 1981 : Tokio) Proceedings of the 13th Conference on Solid State Devices (1982)

Proceedings of the Symposium on Quality Management in Industrial Electrochemistry

Veröffentlicht 1993

Logic Based Embedded DRAM Technologies Targeting Low Voltage and High Speed Operation

von Arai, S.
Veröffentlicht in Handōtai-Shūseki-Kairo-Gijutsu-Shinpojiumu (62 : 2002 : Tokio) Handōtai, Shuseki-Kairo-Gijutsu-62.-Shinpojiumu-kōen-ronbunshū (2002)