Design and FPGA Synthesis of an Efficient Synchronous Counter with Clock-Gating Techniques

von Singh, Saurabh Kumar
Veröffentlicht in NCCS-2019 (5. : 2019 : Ranchi) Nanoelectronics, circuits and communication systems (2021)

Design of High-Speed Binary Counter Architecture for Low-Power Applications

von Gupta, Mangal Deep
Veröffentlicht in NCCS-2019 (5. : 2019 : Ranchi) Nanoelectronics, circuits and communication systems (2021)